Delta-sigma modulator analog-to digital-converters (ADCs) are used almost exclusively in a number of applications such as communications systems, consumer and professional audio, industrial weight scales, and precision measurement devices. Such delta-sigma modulator ADCs can provide both relatively low cost conversion and flexibility in converting low bandwidth input signals.
Typical conventional analog delta-sigma modulators present significant design challenges when implemented in highly-scaled CMOS IC technology optimized for digital circuitry. Such conventional delta-sigma modulators require analog comparators, high-accuracy analog integrators, high-linearity feedback digital-to-analog converters (DACs), and low-noise, low-impedance reference voltage sources. Continuous-time delta-sigma modulators with continuous-time feedback DACs additionally require low jitter clock sources. These circuit blocks are difficult to design as CMOS technology is scaled below the 90 nm node because the scaling tends to worsen supply voltage limitations, device leakage, device nonlinearity, signal isolation, and 1/f noise.
An alternate type of delta-sigma modulator avoids the analog blocks and includes a voltage-controlled ring oscillator (ring VCO) with its inverters sampled at the desired output sample-rate followed by digital circuitry. The ring VCO delta-sigma modulator structure has the same functionality as a first-order continuous-time delta sigma modulator. However, the ring VCO inevitably introduces severe nonlinearity. The dominant, frequency-independent component of this nonlinearity is referred to herein as nonlinear error.
Prior art embodiments of ring VCO delta-sigma modulators have pioneered the establishment of high-performance ADC's within digitally optimized CMOS processes. A technique for correcting the nonlinear error of a ring VCO based ADC entails injecting a zero mean pseudorandom input sequence into a replica conversion path. The output of this path is then correlated according to various combinations of the original input sequence. Over a relatively long period of time, these correlation sums will converge in order to obtain estimated coefficients. These estimated coefficients can then be used to correct the nonlinear error of the signal path and improve the signal to noise-plus-distortion ratio (SNDR) at the ADC output. Unfortunately, this prior art technique requires lengthy digital background calibration to accurately estimate the coefficients to correct gain nonlinearities. Thus, continuous improvements in calculation efficiencies are needed in order to achieve increased calibration speeds and reduced power consumption.